| abstract |
The integrated circuit (1) suppresses leakage currents, which usually take place between neighboring transistors (10, 20) through the unpatterned semiconductor layer (5). In its first layer (3), the circuit (10) comprises electrically conductive tracks (4) which are in contact with the semiconductor layer (5), some of which tracks (4) are in use as source and drain electrodes (14, 15, 24, 25) and are preferably fork-shaped and interdigitated. The suppression of leakage currents is achieved by putting neighboring electrodes (14, 24) in different transistors (10, 20) at the same voltage and by excluding the presence of any other electrically conductive tracks between those neighboring electrodes (14, 24). Interconnect lines (39) carrying input or output signals are positioned in a second layer (7) as much as possible, which second layer (7) comprises electrically conductive tracks (8) and is not in contact with the semiconductor layer (5). The integrated circuit (1) of the invention is very well fitted to contain arrays of NAND structures. |