| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ab054d4fd1810c2c2350c52d00de0add |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-73
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 |
| filingDate |
2016-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4a402c330771ae2382bb87f18a61310
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_442dec78d225c71d1f3480d782ca517b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_100c0c2f66177d53a2525933f1874d2a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed969572dbd7db04382abe9e436d0b2f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df008df80b0dcb0da7bb8407497466f3 |
| publicationDate |
2018-03-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9929149-B2 |
| titleOfInvention |
Using inter-tier vias in integrated circuits |
| abstract |
Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11417629-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11201148-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11455454-B2 |
| priorityDate |
2016-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |