| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78684
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 |
| filingDate |
2016-09-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33b0ef2dd4bd9622eb89f8bba4eda9ca
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_337c73316e986c8c90bc56901d0a2631
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72c790d51683f1946b768304dd683cf1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aca4871baff82c610077f78cb5adefd5 |
| publicationDate |
2018-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9911592-B2 |
| titleOfInvention |
Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure |
| abstract |
A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11158730-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10522342-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020006485-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10395922-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018096835-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11569389-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10833158-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2018294151-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11133421-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10461154-B1 |
| priorityDate |
2015-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |