Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02603 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
filingDate |
2017-12-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2019-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33b0ef2dd4bd9622eb89f8bba4eda9ca http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aca4871baff82c610077f78cb5adefd5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_337c73316e986c8c90bc56901d0a2631 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72c790d51683f1946b768304dd683cf1 |
publicationDate |
2019-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-10395922-B2 |
titleOfInvention |
Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer |
abstract |
A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam. |
priorityDate |
2015-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |