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filingDate 2017-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2018-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9375a3f03b05a540c616b31169301422
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publicationDate 2018-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9870951-B2
titleOfInvention Method of fabricating semiconductor structure with self-aligned spacers
abstract A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.
priorityDate 2015-07-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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