| abstract |
To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. n A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrate. |