http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9842842-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-312 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10811 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-403 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10894 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-403 |
| filingDate | 2015-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb761a089dba691e10fe050a316ea73 |
| publicationDate | 2017-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-9842842-B2 |
| titleOfInvention | Semiconductor memory device and semiconductor device and electronic device having the same |
| abstract | A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V. |
| priorityDate | 2014-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 130.