| abstract |
A floating gate memory cell is provided on a surface of a base semiconductor substrate utilizing a vertical FET processing flow. The floating gate memory cell contains a bottom source/drain region located beneath one end of an epitaxial semiconductor channel material and a top source/drain region located above a second end of the epitaxial semiconductor channel material. A floating gate structure including an inner dielectric material portion, a floating gate portion, an outer dielectric material portion, and a control gate portion is present on each side of the epitaxial semiconductor channel material. |