| abstract |
Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level. |