http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9679771-B1

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0cc90a4cda4760c9a104d5acb5af3019
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331
filingDate 2016-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a494ba6a92141c34ae21f0d08ded11ca
publicationDate 2017-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9679771-B1
titleOfInvention Fabrication and design methods using selective etching and dual-material self-aligned multiple patterning processes to reduce the cut-hole patterning yield loss
abstract Design and fabrication methods to reduce the effect of edge-placement errors in the cut-hole patterning process are invented using selective etching and dual-material self-aligned multiple patterning processes. The invented methods consist of a series of processing steps to decompose the original cut-hole mask into multiple separate masks, pattern the cut holes on the resist to expose certain targeted lines, and selectively etch the exposed targeted lines (formed by dual-material self-aligned multiple patterning processes) without attacking the non-target lines. This invention provides production-worthy methods for the semiconductor industry to continue IC scaling down to sub-10 nm half pitch.
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