Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-4065 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-404 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-70 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4094 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1156 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-404 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-24 |
filingDate |
2016-05-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2017-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_594727610dcd2c320965a69d1fdd291b |
publicationDate |
2017-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-9679629-B2 |
titleOfInvention |
Memory device having wiring layout for electrically connecting to switch and capacitor components |
abstract |
Provided is a memory device having a plurality of memory cells and a refresh circuit. Each of the memory cells is configured to retain multiple data as a potential of a node connected to a gate of a first transistor, one of a source and a drain of a second transistor, and one of electrodes of a capacitor. The refresh circuit is configured to refresh the memory cells. That is, the refresh circuit is configured to determine an interval between refresh operations, estimate a change of the potential of the node due to the leakage of the charge, and provide a refresh potential to the memory cells, where the refresh potential is a sum of the potential read from the node and the potential lost due to the charge leakage. |
priorityDate |
2014-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |