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filingDate 2015-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2017-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bfcb4df95290db82c5919f90b967a64f
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publicationDate 2017-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-9673101-B2
titleOfInvention Minimize middle-of-line contact line shorts
abstract Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
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