Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02263 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02129 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7849 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7624 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
filingDate |
2013-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2017-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_543d1538a8ce3bf1ed24b0d187bc27b1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9824b05e5d21c20311308195c8efa7f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f9eb36341dc1cbe3519adccbe0a1c21 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06e359ce7ccd72a9fb19b322f2ba39d9 |
publicationDate |
2017-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-9553012-B2 |
titleOfInvention |
Semiconductor structure and the manufacturing method thereof |
abstract |
The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide. A method for manufacturing the FinFET includes forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation; oxidizing the fin structure and the layer to transform the layer into a first oxide layer; filling insulating material between adjacent fin structures; and etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10930734-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10734245-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11024711-B2 |
priorityDate |
2013-09-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |