| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8cf8d77ac0eff1767b22d2fb9445b64d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01J2237-334 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01J37-32449
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31122
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31138
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C23F4-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01J37-32422
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-67069
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32136
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01J37-32357 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01J37-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-67
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23F4-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 |
| filingDate |
2015-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0fc976373bab7d13fd7e7342d001b560 |
| publicationDate |
2016-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9431269-B2 |
| titleOfInvention |
Dual chamber plasma etcher with ion accelerator |
| abstract |
The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber. The etching gas and ions react with the surface of the substrate to etch the substrate as desired. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9793126-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11171021-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10134605-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10224221-B2 |
| priorityDate |
2013-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |