| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2014-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_20cb38d9cb42b4a5b0c5a6558bd770e5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4bca646d3b34411235d24e8d804d6b5d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3629a7ff5f398d829c8935e426f28e4 |
| publicationDate |
2016-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9343569-B2 |
| titleOfInvention |
Vertical compound semiconductor field effect transistor on a group IV semiconductor substrate |
| abstract |
Group IV semiconductor devices can be formed on a semiconductor-on-insulator substrate including a handle substrate containing a group IV semiconductor material. A cavity is formed to physically expose a top surface of the handle substrate through a stack, from bottom to top, of a buried insulator layer, a doped semiconductor material portion in a top semiconductor layer, and a dielectric material layer. A gate dielectric is formed around the cavity by a conformal deposition of a dielectric material layer and an anisotropic etch. A lower active region, a channel region, and an upper active region are formed by selective epitaxy processes in, and/or above, the trench and from the top surface of the handle substrate. The selective epitaxy processes deposit a compound semiconductor material. The doped semiconductor material portion functions as the gate of a vertical compound semiconductor field effect transistor. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10020381-B1 |
| priorityDate |
2014-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |