http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9153313-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-40 |
| filingDate | 2014-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3658d963980ac56df4d6be5a7643d15d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_de2584c8c768b0aba8a071f9e507323e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb761a089dba691e10fe050a316ea73 |
| publicationDate | 2015-10-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-9153313-B2 |
| titleOfInvention | Normally-off, power-gated memory circuit with two data retention stages for reducing overhead power |
| abstract | The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit. |
| priorityDate | 2013-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 116.