| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13025 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-743 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525 |
| filingDate |
2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2015-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_642f841cc114d6883904598c6b8f4495
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe8d2838a915e7b1a582eec12f0a6d2e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bd87e962b2e5d42538c5b0d151f9ea9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f9396f2d64a9d4e98b058f736524591
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4a6bf07c042d8c6932f85e7ee7514147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_36f0363697c989b95d2adc7396622e39 |
| publicationDate |
2015-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-9040406-B2 |
| titleOfInvention |
Semiconductor chip with power gating through silicon vias |
| abstract |
A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10224410-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10170578-B2 |
| priorityDate |
2013-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |