Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0fee4475ccb9ebf1a7a38587f3f04b05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1e74277852f1aae0a3ff13f59a65456d http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b399a86e28fd7247b58d50109155e37d http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6e8cfcd128fde70d6e8abf3acfc630e7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a42216e4da3d9e9bb04784f0fa04664a http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e0b4001740dbc19f10e635fc629fcba8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8cce8d4b3993ce9a52968414148cebfa |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 |
filingDate |
2012-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2015-04-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_11d4ebb25172b4510dcae6129feb0778 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_844df79213d97c3e3724de2b84a99448 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_90b5a872181b0c75cd2887aea424c30d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_691f5db3298463f7fadc631a49421a6f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79c812c8aa9cb2f631698d14e7cd91de http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ba0d4dcf3b2e48ce2a8095a72004802 |
publicationDate |
2015-04-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-9018968-B2 |
titleOfInvention |
Method for testing density and location of gate dielectric layer trap of semiconductor device |
abstract |
Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10613131-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11293965-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014247067-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10989664-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11150287-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9255960-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10551325-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11199507-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2017067830-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10591525-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11415617-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10663504-B2 |
priorityDate |
2011-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |