| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ac98f3e6563b96fb18dcdf7300cf3265
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9a5a4244e5207d467e131669f47f0106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6a0536f8231b9f24563921f0924e9de8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8836
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-02 |
| filingDate |
2012-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cb0d0d20629a5fc4431b8da019318a14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c1f63afe29096ca1b45d65fb386deaa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8258652be404f9043d87b9b5f3c384e2 |
| publicationDate |
2014-09-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8824184-B2 |
| titleOfInvention |
Semiconductor memory devices |
| abstract |
A semiconductor memory device includes a stacked structure including a plurality of wordline structures sequentially stacked that each include: a plurality of wordlines with sidewalls and extending in a first direction on the substrate, and a connecting pad extending in a second direction on the substrate and being connected in common to the plurality of wordlines. A plurality of interconnections at a height over the substrate are connected to the connecting pads of the wordline structures, respectively. The device further includes bitlines substantially vertical to a top surface of the substrate and crossing one of the sidewalls of the plurality of wordlines, and memory elements between the bitlines and the plurality of wordlines, respectively. A length of the connecting pad in the second direction is substantially equal to a product of a minimum pitch between the interconnections and a stack number of one of the plurality of wordlines. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10651198-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10879261-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10312256-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11641738-B2 |
| priorityDate |
2011-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |