| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5eddd58b243316108630b75c774b268a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fabd1e96b8bc34befe00b7ae15a7873c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ad9ddd9391508a2733438245a61fbab6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8609910192bf45e2ff8a36f0105bd70c |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66757
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1292
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-60 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28518
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76895 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 |
| filingDate |
2012-08-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bca4d9a4040e6efeacdc93b4428a2f84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_240ff759908d568ba4bd99ac2c4291ce
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d8138723a0346b912046bd75c03134a0 |
| publicationDate |
2014-08-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8796774-B2 |
| titleOfInvention |
Printed non-volatile memory |
| abstract |
A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology. |
| priorityDate |
2006-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |