| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_61f7a81f94ea873a7223550a019b8ae7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5db6237d7f06c1cacb6af4231748fa48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_220d23b670ad294bfee429abfdd60042 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S977-936
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-981
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y99-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42364
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-72 |
| filingDate |
2010-07-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_febf3c5e2ddfb3ba0724d5a6f9a5c987
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bae56b3e8266b2bf651b6fb5a52c796
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e14bf1e1d8ea20c3f5bee432c67525e |
| publicationDate |
2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8674419-B2 |
| titleOfInvention |
Method of forming a CMOS structure having gate insulation films of different thicknesses |
| abstract |
The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9202546-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014252495-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10720433-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9806079-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011101332-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9111909-B2 |
| priorityDate |
1996-04-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |