| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8d629238b5c0aada2fc57fa5dbb59a41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a077aeda737c70a559c084390403771a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1c19f8ceca8ddd300f392e96e0836a75 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-09701
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49861
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-486
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00 |
| filingDate |
2012-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5fea66a08c6a30c84a3e2573fa9e3159
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95be730717b631acfd8c53b4050aecff |
| publicationDate |
2014-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8673689-B2 |
| titleOfInvention |
Single layer BGA substrate process |
| abstract |
Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8940585-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2014206152-A1 |
| priorityDate |
2011-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |