http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8383501-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fd6443076c253deffb905f2db0e670c1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3e204621fd2635b7f13d74ada1fac382 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3ba07e0139cf40192f2c2ecf8666dfe2 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2011-07-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ee2414c1c200a228ee3b0e78cea34057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_32660f771419c48d137a622710903646 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52d7b97dfc54fab9035d67eb048590a3 |
| publicationDate | 2013-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8383501-B2 |
| titleOfInvention | Vertical field effect transistor arrays and methods for fabrication thereof |
| abstract | Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask. |
| priorityDate | 2006-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.