| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c798994916da53bb25d60fe9e82f5f4a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_24ed466534487edec4f31340336bcdbd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_21095a6dc7dac10483add808adb4fa32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_75bea22f147b17ddb02013a4ba83b8ae |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1211
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7841
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-125
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-00 |
| filingDate |
2011-03-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b70f3ee21203e58170dfbfc0146de0b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34d694c73581addc00da238dd9a40879
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ce8158657e3d10117ccecee87d1d2ec6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34341f09f9cdf29198326248200a36ab |
| publicationDate |
2013-01-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-8349670-B2 |
| titleOfInvention |
Selective floating body SRAM cell |
| abstract |
A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11355499-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11641729-B2 |
| priorityDate |
2009-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |