http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8323990-B2

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
filingDate 2007-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2012-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8d47c459e7a5381b4ebaf485807c08a5
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publicationDate 2012-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-8323990-B2
titleOfInvention Reliability test structure for multilevel interconnect
abstract Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011074459-A1
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priorityDate 2006-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 27.