http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8263493-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d5cb49987e597f3b602229b65c05f3e6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_81bbed339049c84138a09736b647d40e http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bb712c08712c64caf1d31e628a714597 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_13dd7a0e8178217b88296da2a9c922e4 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4763 |
| filingDate | 2009-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2012-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0b0f9e8e5f8180b583ba0aafe0ce1f6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f805e82acfe52cb1104b94bfd3aba49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_299441b6b31b4a80dd3bc4c958d83f6f |
| publicationDate | 2012-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-8263493-B2 |
| titleOfInvention | Silicon chip having through via and method for making the same |
| abstract | The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process. |
| priorityDate | 2009-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.