http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7968937-B2

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filingDate 2008-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2011-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f55ba120411d0a9c38eecb27efa24fdd
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publicationDate 2011-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7968937-B2
titleOfInvention Vertical transistor and array with vertical transistors
abstract A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates.
priorityDate 2008-08-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 25.