| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76807 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3148
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3185
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-469 |
| filingDate |
2007-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2010-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89d5e2c63354d20c79e1d9e937ccef42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0324d4b85e2401bf9d6b314425d1bff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2c493d32e44a9416958ea915c13fa179
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_45324c91d518172140cf739f8ad35b2e |
| publicationDate |
2010-03-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-7682989-B2 |
| titleOfInvention |
Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion |
| abstract |
In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric. |
| priorityDate |
2007-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |