http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7638401-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-318 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823892 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-09 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| filingDate | 2008-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2009-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a450a86e149764135f8c9a56e8056274 |
| publicationDate | 2009-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7638401-B2 |
| titleOfInvention | Memory device with surface-channel peripheral transistors |
| abstract | A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates 58 are formed. These gates 58 are classed into three groups; namely, first conductivity type peripheral gates 58 p , second conductivity type peripheral gates 58 n , and array gates 58 a . The array gates 58 a and the first conductivity type peripheral gates 58 n are masked such that the second conductivity type peripheral gates 58 p remain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates 58 p , while simultaneously doping a first and a second source/drain region 84 adjacent each of the second conductivity type peripheral gates 58 p . The second conductivity type peripheral gates 58 p are then masked such that the first conductivity type peripheral gates 58 n remain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates 58 n , while simultaneously doping a first and a second source/drain region 82 adjacent each of the first conductivity type peripheral gates 58 n. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010019249-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8120072-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9171948-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9202871-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8723235-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2013270621-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11311605-B2 |
| priorityDate | 1997-10-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.