http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7439165-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d5059ed67382a0c8e7af5f58eb2b787f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78687 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823878 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-38 |
| filingDate | 2005-04-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2008-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_383c48b66453f2101f7869b7e1d9fe24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17dd9271d04d87d8ece3c701a3752e1b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_348cec5267ad90cba53c1b87ca4f7236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1b6880b638fa858f031158de8c8f67a1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c687b6480c9b8810cc352c785627528 |
| publicationDate | 2008-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-7439165-B2 |
| titleOfInvention | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device |
| abstract | A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon layers is initiated. A semiconductor alloy layer is deposited followed by an oxidation procedure used to segregate a germanium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the underlying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the subsequently deposited silicon-germanium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions' germanium concentration. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9343302-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8936974-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011008937-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8722478-B2 |
| priorityDate | 2005-04-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 53.