| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3a62c92e56568bd104089aac22ca487b |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76232 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate |
2002-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2004-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92d3e54b9bcae87bd892d8ce7365628b |
| publicationDate |
2004-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-6696348-B1 |
| titleOfInvention |
Wide neck shallow trench isolation region to prevent strain relaxation at shallow trench isolation region edges |
| abstract |
The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7247534-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004209437-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-8951885-B2 |
| priorityDate |
2002-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |