http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7233513-B2

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filingDate 2005-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2007-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43c2d1c754de56abc15315841e813a4d
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publicationDate 2007-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-7233513-B2
titleOfInvention Semiconductor memory device with MOS transistors each having floating gate and control gate
abstract A semiconductor memory device includes memory cells, a memory cell array, word lines, a row decoder, first metal wiring layers, and metal wiring lines. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. Each word line is formed by connecting commonly the control gates in a same row. The row decoder selects any one of the word lines. The first metal wiring layers are provided for the word lines in a one-to-one correspondence. The first metal wiring layers are electrically connected to the corresponding ones of the word lines and transmit a first row select signal for the row decoder to select one of the word lines. The metal wiring lines are formed at a plurality of levels. The first metal wiring layers are made of the metal wiring lines located at the level of the lowest layer.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010001404-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2011221067-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2009122609-A1
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priorityDate 2004-10-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 47.