http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6815760-B2

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
filingDate 2002-07-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2004-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d25258c1a71b96e247a3aef8a5046041
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d28e980e4baa75ecea894db8bb94dc5b
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publicationDate 2004-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6815760-B2
titleOfInvention Nonvolatile memory structures and fabrication methods
abstract To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.
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