http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6518174-B2

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 2000-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_745a19c0ed954935a6964c7a2257a5c4
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publicationDate 2003-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-6518174-B2
titleOfInvention Combined resist strip and barrier etch process for dual damascene structures
abstract A method of etching a stack is provided. Generally, a trench patterned resist layer is placed over a dielectric layer of the stack. A trench is partially etched into the dielectric layer. A simultaneous stripping of the trench patterned resist layer, etching the barrier layer, and etching the trench is then performed. As a result an etch stack may be provided with less damage. The method may be used to provide a dual damascene structure. The dual damascene structure may be provided by etching a via before placing the trench patterned resist layer over the dielectric layer of the stack.
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Total number of triples: 47.