| abstract |
In order to form a self-aligned damascene gate which enables the resistance of the gate to be reduced, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. The dielectric layer is polished for planarity using a chemical-mechanical-polishing (CMP) technique or the like. A gate mask is then used to pattern the dielectric, the interlayer dielectric (ILD) is etched, and the resist is stripped. A gate dielectric is deposited in the form of a CVD nitride, oxynitride, or stacked nitride oxide ONO, or the like. Polysilicon is then deposited over the dielectric, doped by implantation, and annealed. A silicon rich silicide layer is then deposited after which CMP or the like is used to remove the superfluous portions of the silicide, doped polysilicon and gate oxide layers down to the dielectric level. The surface is then cleaned and annealed to induce the excess silicon to migrate to the surface of the remaining plug-like portion of silicon rich suicide material and form a thin silicon layer thereon. A contact mask is then formed and contact areas etched. The polysilicon layer at the gate site and the silicon exposed at the contact site are then reacted to form salicides. |