Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-022 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3122 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3144 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02282 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02321 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76825 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-314 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-312 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
filingDate |
1999-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2001-02-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_02760c6e9fb713158a40eff3151ea297 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_69b24314e0b6e1bd96393adbc9ece1b1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d7dcad1357696a59204baf168c164fc |
publicationDate |
2001-02-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-6184123-B1 |
titleOfInvention |
Method to prevent delamination of spin-on-glass and plasma nitride layers using ion implantation |
abstract |
A method of forming an integrated circuit device using ion implantation to improve the adhesion of plasma nitride to spin-on-glass is achieved. Semiconductor device structures are provided in and on a substrate where conductive connections are planned between the device structures and planned conductive traces overlying a planned interlevel dielectric layer. An insulating oxide layer is deposited overlying the device structures. A spin-on-glass layer is coated overlying the insulating oxide layer. The spin-on-glass layer is dried. The spin-on-glass layer is ion implanted to form an amorphous, silicon rich, adhesion layer at the top surface of the spin-on-glass layer. The spin-on-glass layer is cured. A first plasma-enhanced silicon nitride layer deposited overlying the adhesion layer of the spin-on-glass and completing the interlevel dielectric layer. Via openings are etched through to the top surfaces of the semiconductor device. A conductive layer is deposited to fill the via openings and is etched to form the conductive traces. A second plasma-enhanced silicon nitride layer is deposited to complete the integrated circuit. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6764774-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6828679-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104810275-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113380620-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104810277-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2010261036-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104835784-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6797605-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6407007-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6423652-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003197173-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2005032392-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2007032060-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113380620-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2004219799-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008026594-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104810277-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7078333-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7670961-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104810275-B |
priorityDate |
1999-08-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |