| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02304
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31612
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 |
| filingDate |
1997-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1998-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_29cce68102b88203842d1e25f5c59417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_27d5e02520f3050ff3402fd7bc1a17f6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4f445c398d8f82dcb05d177d13daa05 |
| publicationDate |
1998-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-5804498-A |
| titleOfInvention |
Method of making an underlayer to reduce pattern sensitivity of ozone-TEOS |
| abstract |
An improved method of ozone-TEOS deposition with reduced pattern sensitivity and improved gap filling capability is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines wherein the conducting lines are dense in some portions of the semiconductor substrate and sparse in other portions of the substrate and wherein gaps are formed between the conducting lines. A nucleation layer is formed by depositing a first pattern sensitivity reducing layer over the surfaces of the conducting layer and then depositing a first oxide layer overlying the first dielectric layer. A second oxide layer is deposited over the nucleation layer wherein the gap is filled by the second oxide layer and the fabrication of integrated circuit is completed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6489083-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6455444-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6093593-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6511923-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6184123-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113451134-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113451134-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6211570-B1 |
| priorityDate |
1995-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |