| abstract |
A process for fabricating a MOSFET device has been developed featuring a polycide gate structure, comprised of a metal silicide component, overlying a polysilicon component, and with the metal silicide shape intentionally fabricated to be narrower than the underlying polysilicon shape. This polycide configuration is obtained using an isotropic RIE procedure for the metal silicide shape, while using an anisotropic RIE procedure for the definition of the polysilicon shape. The undercut metal silicide shape can now accommodate a thermally grown oxide layer, thicker than the thermally grown oxide formed on the underlying, straight walled polysilicon shape, and thus allowing a lightly doped source and drain region, and the subsequent MOSFET channel length, to be defined by the thin oxide, on the sides of the straight walled polysilicon shape. |