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filingDate 1997-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1999-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7eb213879a3d808876e13769e95d55d7
publicationDate 1999-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-5940726-A
titleOfInvention Method for forming an electrical contact for embedded memory
abstract An improved method of forming a good electrical contact within a deep contact opening is described. Semiconductor device structures in and on a semiconductor substrate are covered with a dielectric layer. A contact opening is etched through the dielectric layer to the semiconductor substrate where the good electrical contact is to be made wherein the contact opening has an aspect ratio greater than one and wherein contaminants are found on the surface of the semiconductor substrate at the bottom of the contact opening. A titanium layer is deposited overlying the dielectric layer and within the contact opening. Silicon ions are implanted into the substrate at a vertical implant wherein the peak implant dose is targeted for the interface between the titanium layer and the semiconductor substrate within the contact opening. Thereafter, the substrate is annealed whereby the titanium layer is transformed into titanium silicide and whereby the contaminants are broken up and thereafter depositing a metal layer within the contact opening to complete a good electrical contact in the fabrication of an integrated circuit device.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2008014352-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6069074-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7375027-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2003186532-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006160343-A1
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6171938-B1
priorityDate 1997-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 46.