| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2c78d80e9d323ad7c79518c80e0b8d16 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate |
1997-05-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
1999-07-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3005a99c318edb241bac0fbb9cb65581
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34f992243be21ab7ec9083ea267748c7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd792126045b4623313fab8f884d7d66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9c33f0fc87a5b0df13dd17cf66109dfc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_601192bf483a4d48b43aaf85bbe21621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da33485bcd1397c9d791bf037f983666 |
| publicationDate |
1999-07-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-5930627-A |
| titleOfInvention |
Process improvements in self-aligned polysilicon MOSFET technology using silicon oxynitride |
| abstract |
Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost. |
| isCitedBy |
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| priorityDate |
1997-05-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |