| abstract |
A process has been developed in which a deep submicron MOSFET device has been fabricated, featuring a local, narrow threshold voltage adjust region, in a semiconductor substrate, with the local, narrow threshold voltage adjust region, self aligned to an overlying, narrow tungsten-polysilicon gate structure. The process consists of forming a narrow hole opening in an insulator layer, where the insulator layer overlies a polysilicon layer and a gate insulator layer. An ion implantation procedure, through the polysilicon layer, and gate insulator layer, is used to place a narrow threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. Selective deposition of tungsten results in the creation of a tungsten gate structure, in the narrow hole opening, on the top surface of the polysilicon layer. Patterning of the polysilicon layer, using the overlying tungsten gate structure as a mask, results in an polysilicon gate structure, underlying the tungsten gate structure, in the narrow hole opening. The composite narrow tungsten-polysilicon gate structure is self aligned to the underlying, local, narrow threshold voltage adjust region. |