Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10S438-958 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28512 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
filingDate |
1994-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
1995-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e67de89ed85a487b525aa5bc88586331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_518b9c7c4b6eebe1f587affc05e4f17a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a3931e47382401f7f845a06a8ac01c88 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecbb142be3de256d787e9e6a56443b0d |
publicationDate |
1995-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-5461254-A |
titleOfInvention |
Method and resulting device for field inversion free multiple layer metallurgy VLSI processing |
abstract |
There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5786638-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6303953-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5926741-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5880518-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2006151826-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-100350604-C http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6048763-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6057581-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6396089-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2016351493-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5844274-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6010935-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5733797-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-6319849-B1 |
priorityDate |
1991-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |