http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5367651-A

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-443
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-441
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-45
filingDate 1992-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 1994-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d31d7283654bbe4bfcf7e103a83f613
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65ae23a3dd222a38b370fa069a2bf8ec
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e322d3e22ff1c16ae1d81ef63432a089
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4416343e865fa6fd529cbb47b4bd8bd6
publicationDate 1994-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-5367651-A
titleOfInvention Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling
abstract An improved register allocator, an improved instruction scheduler, an instruction combiner, and an improved loop unroller is provided to the code generator of a compiler of a computer system. Both the improved instruction scheduler and the improved loop unroller support a "preliminary" and a "final" mode of operation. Upon invocation, the improved register allocator determines and prioritizes regions of the program being compiled. Next, the improved register allocator, in cooperation with the improved instruction scheduler, the instruction combiner, and the improved loop unroller, determines the optimal partitioning for global and local registers for each region. Then, the improved register allocator allocates registers to each region based on the determined number of global registers for the region. After allocating registers for each region, the improved register allocator merges the regions together. The improved loop unroller and the improved instruction scheduler are then invoked successively in "final" mode to unroll the various loops and schedule the instructions being generated.
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Total number of triples: 105.