| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_68f6d4ec23bb81fda9c37314ff90b20f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-452 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate |
2001-10-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54ef196dec06f973419404ae8c015543 |
| publicationDate |
2002-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2002133813-A1 |
| titleOfInvention |
Hardware supported software pipelined loop prologue optimization |
| abstract |
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating an initiation interval time (IN) for a pipelined stage of the loop. A loop operation time latency (Tld) and a number of loop operations (Np) from the pipelined stages to peel based on IN and Tld is then determined. The loop operation is peeled Np times and copied before the loop in the software code. A vector of registers is allocated and the results of the peeled loop operations and a result of an original loop operation is assigned to the vector of registers. Memory addresses for the results of the peeled loop operations and original loop operation are also assigned. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7856629-B2
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9733913-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-7827542-B2 |
| priorityDate |
1999-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |