| abstract |
In the fabrication of an interconnection package for a plurality of semiconductors or integrated circuit chips wherein a multi-layered glass or glass-ceramic superstructure with a multi-layered distribution of planar conductors is formed by a process forming vertical conductive interconnection or studs between planar conductor layers, by pre-forming a via configuration in each glass or glass-ceramic layer at the interconnection points followed by depositing the conductive studs therein. The via configuration is formed by defining a desired pattern of vias, and ablating the vias through the top of and through the glass or glass-ceramic layer, using an ultraviolet laser. The vias may be stepped-shoulder or counter-bored by using a two mask operation. |