| abstract |
The present invention relates to the method of making a memory device of the metal insulator silicon field effect transistor structure having a gate region combining a chemically formed thin oxide layer and a second insulating layer, such as silicon nitride, and to the novel product which results from this method. The method entails the step of chemically oxidizing the surface of the silicon channel region by a self-limiting process to form a thin porous oxide, and a nitriding step which is conducted under conditions producing optimum interface traps and minimum initial charge. Both steps lead to highly reproducible devices. The method is readily applied to large arrays of devices, offering ease of manufacture and close device parameter control. One form of the process provides for the production of both memory and read-out devices appropriate in an array. |