| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-743
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1207
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823487
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2019-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_39d3cd30365622b0081dee9e814a118d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eab04d970549ef9458baa933a5c4693c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e08d91ff19fce642276d4cd68e163970 |
| publicationDate |
2020-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-2020411388-A1 |
| titleOfInvention |
Stacked vertical transport field effect transistor contact formation |
| abstract |
A method for forming a semiconductor structure is provided. The method including epitaxially growing a first source drain on the semiconductor structure between a first lower fin in a first region of the semiconductor structure and a second lower fin in a second region of the semiconductor structure, forming a first spacer layer on the first source drain, where a lower horizontal surface of the first spacer layer is coplanar with an upper horizontal surface of the first source drain, forming a lower gate stack surrounding the first lower fin and surrounding the second lower fin on exposed surfaces of the semiconductor structure, where a lower horizontal surface of the gate stack is coplanar with an upper horizontal surface of the first spacer layer, forming an interlayer dielectric on exposed surfaces of the first spacer layer. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021043522-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11574845-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11502199-B2 |
| priorityDate |
2019-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |