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filingDate 2020-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5cb24b2cfcec8d620b1b9fc4cce3311
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publicationDate 2020-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-2020219868-A1
titleOfInvention Esd hard backend structures in nanometer dimension
abstract Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11621261-B2
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Total number of triples: 39.