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filingDate 2018-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2020-04-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10629588-B2
titleOfInvention ESD hard backend structures in nanometer dimension
abstract Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
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