| abstract |
A semiconductor device includes an insulated gate field effect transistor connected in series with a FET. The FET includes parallel conductive layers. A substrate of first conductivity type extends under both transistors, with a first layer of a second conductivity type over the substrate. On this first layer are arranged conductive layers with channels formed by the first conductivity type doped epitaxial layers with layers of a first conductivity type on both sides. The uppermost layer of the device is thicker than the directly underlying several parallel conductive layers. The field effect transistor, JFET, is isolated with deep poly trenches of first conductivity type, DPPT, on the source side of the JFET. The insulated gate field effect transistor is isolated with deep poly DPPT trenches on both sides. A further isolated region with logic and analog control functions is isolated with deep poly DPPT trenches on both sides. |